The present invention relates to an integrated injection logic.
An integrated injection logic (I.sup.2 L) does not require isolation between semiconductor elements even though the integrated injection logic is a bipolar transistor. Therefore, such a semiconductor device is highly integrated. Further, since a lateral pnp transistor is used as a current source or load, power consumption is greatly reduced.
An integrated injection logic (to be referred to as an I.sup.2 L hereinafter) comprises an n.sup.+ -type semiconductor substrate, an n-type epitaxial layer which is formed on the semiconductor substrate, a p-type injector region which is formed in this epitaxial layer, a p-type layer which is formed in the epitaxial layer, and a plurality of n-type regions which are formed in the p-type layer. In the I.sup.2 L with the above arrangement, minority carriers are excessively accumulated in the n-type expitaxial layer and the p-type layer which is formed in the n-type epitaxial layer when the I.sup.2 L operates, reducing the switching speed of the device.
In order to solve this problem, a device is disclosed in Japanese Patent Publication (KOKOKU)JP, B2,55-32225. The present invention provides a device which further improves the device proposed in the above publication.